Charla: ESD protection design for integrated circuits

CHARLA: ESD PROTECTION DESIGN FOR INTEGRATED CIRCUITS

Fecha: jueves 31 de mayo
Hora: 10h00
Lugar: D128 (Aula Magna)
Publico: Para los estudiantes de la maestría en Nanoelectrónica IEEE (profe. y estudiantes)

ESD failure is one of the most devastating reliability problems to ICs and microelectronics products. Recent advances in IC technologies and designs make on-chip ESD protection designs extremely challenging. For more than five decades, vast efforts have been devoted to research and development in ESD protection designs. This lecture discusses all aspects on ESD protection designs for ICs, including ESD fundamentals, ESD protection solutions, mixed-mode ESD simulation-design methods, and ESD-IC co-design techniques. Real-world ESD protection circuit design examples will be discussed.

Received the BSEE degree from Tsinghua University, China, and the PhD EE degree from State University of New York at Buffalo, USA, in 1985 and 1996, respectively. From 1995 to 1998, he was with National Semiconductor Corporation in the Silicon Valley. From 1998 to 2007, He was a Professor of Electrical and Computer Engineering at the Illinois Institute of Technology, Chicago. Since 2007, He has been a Professor of Electrical and Computer Engineering at the University of California, Riverside, where he is Director for the Laboratory for Integrated Circuits and Systems, and Director for the University of California Center for Ubiquitous Communications by Light. His research covers Analog/Mixed-Signal/RF ICs, Integrated Design-for-Reliability, 3D Heterogeneous Integration, IC CAD and Modelling, Biomedical Electronics, Emerging Nano Devices and Circuits, and LED-based Visible Light Communications

Wang received the NSF CAREER Award. He published 1 book and more than 250 papers, and holds 15 US patents. Wang was editor and guest editor for IEEE Electron Device Letters, IEEE Transactions on Circuits and Systems I, IEEE Transactions on Circuits and Systems II, IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices and IET Journal of Engineering. He has been an IEEE Distinguished Lecturer for IEEE Electron Devices Society, IEEE Solid-State Circuits Society and IEEE Circuits and Systems Society. He is Sr. Past President (2018-2019), and was Jr. Past President (2016-2017) and President (2014-2015) of IEEE Electron Devices Society. He was Chair of the IEEE CAS Analog Signal Processing Technical Committee (ASPTC) and committee member for the SIA International Technology Roadmap for Semiconductor (ITRS). He is IEEE 5G Initiative member. He is a member of IEEE Fellow Committee. He was General Chair (2016) and TPC Chair (2015) for IEEE RFIC Symposium. He served as committee member for many IEEE conferences, including IEDM, EDTM, BCTM, ASICON, IEDST, ICSICT, CICC, RFIC, APC-CAS, ASP-DAC, ISCAS, IPFA, ICEMAC, NewCAS, ISTC,